//-----------------------------------------------------------------------------
//  
//  Copyright (c) 2013
//
//  Project  : GUANGLU-10G-STM4
//  Module   : 
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths



module    STM4_TOP(
   input                  CLK_SYS_CLK155M52,
   input                  CLK_RF_CLK,
   input                  CLK_RF_CLK25M,

   input                  BP_RF_CLK155M52,
   input                  BP_RXD_0,
   input                  BP_RXD_1,
   output                 BP_TXD_0,
   output                 BP_TXD_1,
   input                  BP_FP_0,
   input                  BP_FP_1,

   input                  OPT_RXD_0,
   input                  OPT_RXD_1,
   input                  OPT_RXD_2,
   input                  OPT_RXD_3,
   input                  FPGA_CPLD1,           //  OPT_SD_0,
   input                  FPGA_CPLD2,			// OPT_SD_1,
   input                  FPGA_CPLD3,			// OPT_SD_2,
   input                  FPGA_CPLD4,			// OPT_SD_3,
   output                 OPT_TXD_0,
   output                 OPT_TXD_1,
   output                 OPT_TXD_2,
   output                 OPT_TXD_3,

   input[19:0]            CPU_A,
   inout[15:0]            CPU_D,
   input                  CPU_RW,
   input                  CPU_CSN,
   input                  CPU_RST_N,
   output                 CPU_INT,

   output                 test_led0,
   output                 test_led1,
   output                 test_led2,
   output                 test_led3,

   output reg              LINE_OLB_CLK_1_FPGA,
   output               LINE_OLB_CLK_2_FPGA,

   output                 DEBUG_TP2,
   output                 DEBUG_TP3,
   output                 DEBUG_TP4,
   output                 DEBUG_TP5,
   output                 DEBUG_TP6,
   output                 DEBUG_TP7
   );



// AUPP output signal
wire                      AUPP_0_FP;
wire[7:0]                 AUPP_0_DATA;
wire                      AUPP_1_FP;
wire[7:0]                 AUPP_1_DATA;
wire                      AUPP_2_FP;
wire[7:0]                 AUPP_2_DATA;
wire                      AUPP_3_FP;
wire[7:0]                 AUPP_3_DATA;

// backplane bus mux output signals
wire                      BMUX_FP;
wire[15:0]                BMUX_OUT_DATA;




wire                      GTM_RESET;
wire                      GTM_CLK155M52;
wire                      GS_CLK77M76;
wire                      GS_CLK38M88;
wire                      GS_CLK19M44;

wire                      CDR_RF_CLK0, CDR_RF_CLK45, CDR_RF_CLK90, CDR_RF_CLK135;

wire                      RX_CDR_CLK19M_0, RX_CDR_CLK19M_1, RX_CDR_CLK19M_2, RX_CDR_CLK19M_3;
wire[7:0]                 RX_CDR_DATA_0, RX_CDR_DATA_1, RX_CDR_DATA_2, RX_CDR_DATA_3;
wire                      TX_CDR_DATA155M_0, TX_CDR_DATA155M_1, TX_CDR_DATA155M_2, TX_CDR_DATA155M_3;

reg[31:0]                 debug_second_cnt25m;
reg                       debug_reset;
reg[31:0]                 debug_second_cnt155m;


reg[15:0]                 debug_reset_cnt;

// Internal MPI interface signals

wire[1:0]               clock_output_sel;

assign OPT_SD_0 = FPGA_CPLD1;
assign OPT_SD_1 = FPGA_CPLD2;
assign OPT_SD_2 = FPGA_CPLD3;
assign OPT_SD_3 = FPGA_CPLD4;
   


assign LINE_OLB_CLK_2_FPGA = LINE_OLB_CLK_1_FPGA;



always @( * ) begin
   case(clock_output_sel[1:0])
   2'b00    :   LINE_OLB_CLK_1_FPGA <= RX_CDR_CLK19M_0_8K | OPT_SD_0;
   2'b01    :   LINE_OLB_CLK_1_FPGA <= RX_CDR_CLK19M_1_8K | OPT_SD_1;
   2'b10    :   LINE_OLB_CLK_1_FPGA <= RX_CDR_CLK19M_2_8K | OPT_SD_2;
   2'b11    :   LINE_OLB_CLK_1_FPGA <= RX_CDR_CLK19M_3_8K | OPT_SD_3;
   default  :   ;
	endcase
end

FP8K_GEN U0_FP8K_GEN(
    .reset_h        (GTM_RESET),
    .clk19m         (RX_CDR_CLK19M_0),
    .fp8k           (RX_CDR_CLK19M_0_8K)
    );
FP8K_GEN U1_FP8K_GEN(
    .reset_h        (GTM_RESET),
    .clk19m         (RX_CDR_CLK19M_1),
    .fp8k           (RX_CDR_CLK19M_1_8K)
    );
FP8K_GEN U2_FP8K_GEN(
    .reset_h        (GTM_RESET),
    .clk19m         (RX_CDR_CLK19M_2),
    .fp8k           (RX_CDR_CLK19M_2_8K)
    );
FP8K_GEN U3_FP8K_GEN(
    .reset_h        (GTM_RESET),
    .clk19m         (RX_CDR_CLK19M_3),
    .fp8k           (RX_CDR_CLK19M_3_8K)
    );

    
    

    
// assign OPT_TXD_0    = OPT_RXD_0;
// assign OPT_TXD_1    = OPT_RXD_1;
// assign OPT_TXD_2    = OPT_RXD_2;
// assign OPT_TXD_3    = OPT_RXD_3;

   wire[7:0]     DEBUG_KEEP_IN;
   wire[7:0]     DEBUG_KEEP_OUT;

wire                   debug_aupp_fp;
wire[7:0]              debug_aupp_data;

   wire                     debug_bp_fp;
   wire[7:0]                debug_bp_data;
  
    
    
always @( posedge CLK_RF_CLK25M ) begin
   if ( debug_reset_cnt[15:0] !=16'hffff )
      debug_reset_cnt[15:0]                     <= debug_reset_cnt[15:0] +16'd1;
end

always @( posedge GTM_RESET or posedge CLK_RF_CLK25M) begin
   if ( GTM_RESET==1'b1 ) begin
      debug_second_cnt25m               <= 0;
   end
   else begin
      if ( debug_second_cnt25m[31:0]==32'd24999999 ) begin
         debug_second_cnt25m            <= 0;
         debug_reset                    <= 1;
      end
      else begin
         debug_second_cnt25m            <= debug_second_cnt25m +1;
         debug_reset                    <= 0;
      end
   end
end

always @( posedge debug_reset or posedge CLK_SYS_CLK155M52) begin
   if ( debug_reset==1'b1 )
      debug_second_cnt155m              <= 0;
   else
      debug_second_cnt155m              <= debug_second_cnt155m +1;
end
  assign DEBUG_TP7 = debug_second_cnt155m[31];


  assign DEBUG_TP2 = CPU_RST_N;
  assign DEBUG_TP3 = CLK_SYS_CLK155M52;

assign test_led0 = lock_ind_led0;
assign test_led1 = lock_ind_led1;
assign test_led2 = LINE_OLB_CLK_1_FPGA;
assign test_led3 = 1'b0;

//  ++++++++++++++++++++++++++++ Global Clocks and timing signals generate  +++++++++++++++++++++++++++++  //
GCK_PLL                              INST_GCK_PLL(
   .areset                           ( GTM_RESET ),
   .inclk0                           ( CLK_SYS_CLK155M52 ),
   .c0                               ( GTM_CLK155M52 ),
   .c1                               ( GS_CLK77M76 ),
   .c2                               ( GS_CLK38M88 ),
   .c3                               ( GS_CLK19M44 ),
   .locked                           ( lock_ind_led0 )
   );
CDR_PLL                              INST_CDR_PLL(
   .areset                           ( GTM_RESET ),
   .inclk0                           ( CLK_SYS_CLK155M52 ),
   .c0                               ( CDR_RF_CLK0 ),
   .c1                               ( CDR_RF_CLK45 ),
   .c2                               ( CDR_RF_CLK90 ),
   .c3                               ( CDR_RF_CLK135 ),
   .locked                           ( lock_ind_led1 )
   );




/*STM4_MPI                           INST_STM4_MPI(
   .GLB_RESET                      ( GTM_RESET ),
   .GLB_CLOCK77M                   ( GS_CLK77M76 ),
   .CPU_ADDR                       ( CPU_A[15:0] ),
   .CPU_RW                         ( CPU_RW ),
   .CPU_CSN                        ( CPU_CS ),
   .CPU_DATA                       ( CPU_D[15:0] ),

   .MPI_WDATA                      ( MPI_WDATA[15:0] ),
   .MPI_RDATA                      ( MPI_RDATA[15:0] ),
   .MPI_RDEN                       ( MPI_RDEN ),
   .MPI_WREN                       ( MPI_WREN ),
   .MPI_ADDR                       ( MPI_ADDR[15:0]),
   .MPI_CSB                        ( MPI_CSB[31:0])
    ) ;
  assign MPI_RDATA[15:0]  = MPI_RD_GLOBAL_REGS[15:0] | MPI_RD_FRM_0[15:0] | MPI_RD_FRM_1[15:0];

STM4_GLOBAL_REGS                   INST_GLOBAL_REGS(
   .reset                          ( GTM_RESET ),
   .clock77M                       ( GS_CLK77M76 ),
   .ADDRESS                        ( CPU_A[7:0] ),
   .CS                             ( MPI_CSB[0] ),                // 0x0000-0x00ff

   .WREN                           ( MPI_WREN ),
   .WDIN_MPI                       ( MPI_WDATA[15:0] ),
   .RDOUT_MPI                      ( MPI_RD_GLOBAL_REGS[15:0] ),

   .DDR2INIT                       ( ),
   .EX_RESET_VECTOR                ( ),
   .ADD_SEL                        ( ),

   .TL2RLOOPM0                     ( ),
   .TL2RLOOPM1                     ( ),
   .RL2TLOOPM0                     ( ),
   .RL2TLOOPM1                     ( ),

   .CLK_SRC_SELC0                  (clock_output_sel[1:0] ),
   .CLK_SRC_SELC1                  ( ),
   .CLK_SRC_SELC2                  ( ),

   .E1_FFERR_CHN                   ( ),
   .E1M0_FFERR_EN                  ( ),
   .E1M1_FFERR_EN                  ( ),
   .E1M0_FFERR                     ( ),
   .E1M1_FFERR                     ( ),

   .E1SYNC                         ( ),

  // interrupt request signals
   .MPI_IRQ_HDLC                   ( ),
   .MPI_TOP_IRQ                    ( ),
   .DEBUG_KEEP_IN                  ( DEBUG_KEEP_IN ),
   .DEBUG_KEEP_OUT                 ( DEBUG_KEEP_OUT )
    ) ;
*/


wire                  rxfp_0, rxfp_1, rxfp_2, rxfp_3;
wire                  rxj1_0, rxj1_1, rxj1_2, rxj1_3;
wire                  rxspe_0, rxspe_1, rxspe_2, rxspe_3;
wire[7:0]             rxdata_0, rxdata_1, rxdata_2, rxdata_3;

wire                  txfp_0, txfp_1, txfp_2, txfp_3;
wire                  txj1_0, txj1_1, txj1_2, txj1_3;
wire                  txspe_0, txspe_1, txspe_2, txspe_3;
wire[7:0]             txdata_0, txdata_1, txdata_2, txdata_3;


/*RLCDR                          INST_RLCDR_0(
   .RESET                      ( GTM_RESET ),
   .TL2RLOOPM0                 ( 1'b0 ),
   .TL2RLOOPM1                 ( 1'b0 ),
   .RL2TLOOPM0                 ( 1'b0 ),
   .RL2TLOOPM1                 ( 1'b0 ),
   .CLK116P0                   ( CDR_RF_CLK0 ),
   .CLK116P45                  ( CDR_RF_CLK45 ),
   .CLK116P90                  ( CDR_RF_CLK90 ),
   .CLK116P135                 ( CDR_RF_CLK135 ),
   .RLD155M0                   ( OPT_RXD_0 ),
   .RLD155M1                   ( OPT_RXD_1 ),
// .TLD155M0                   ( OPT_TXD_0 ),
// .TLD155M1                   ( OPT_TXD_1 ),
   .TDFRM155M0                 ( TX_CDR_DATA155M_0 ),
   .TDFRM155M1                 ( TX_CDR_DATA155M_1 ),

   .RCVWE                      (  ),
   .RCVWCTL                    (  ),
   .RCVWDATA                   (  ),

   .Data19M0                   ( RX_CDR_DATA_0[7:0] ),
   .Clock19M0                  ( RX_CDR_CLK19M_0 ),
   .Data19M1                   ( RX_CDR_DATA_1[7:0] ),
   .Clock19M1                  ( RX_CDR_CLK19M_1 ),
   .clk_8k_0                   (  ),
   .clk_8k_1                   (  )
    ) ;
RLCDR                          INST_RLCDR_1(
   .RESET                      ( GTM_RESET ),
   .TL2RLOOPM0                 ( 1'b0 ),
   .TL2RLOOPM1                 ( 1'b0 ),
   .RL2TLOOPM0                 ( 1'b0 ),
   .RL2TLOOPM1                 ( 1'b0 ),
   .CLK116P0                   ( CDR_RF_CLK0 ),
   .CLK116P45                  ( CDR_RF_CLK45 ),
   .CLK116P90                  ( CDR_RF_CLK90 ),
   .CLK116P135                 ( CDR_RF_CLK135 ),
   .RLD155M0                   ( OPT_RXD_2 ),
   .RLD155M1                   ( OPT_RXD_3 ),
// .TLD155M0                   ( OPT_TXD_2 ),
// .TLD155M1                   ( OPT_TXD_3 ),
   .TDFRM155M0                 ( TX_CDR_DATA155M_2 ),
   .TDFRM155M1                 ( TX_CDR_DATA155M_3 ),

   .RCVWE                      (  ),
   .RCVWCTL                    (  ),
   .RCVWDATA                   (  ),

   .Data19M0                   ( RX_CDR_DATA_2[7:0] ),
   .Clock19M0                  ( RX_CDR_CLK19M_2 ),
   .Data19M1                   ( RX_CDR_DATA_3[7:0] ),
   .Clock19M1                  ( RX_CDR_CLK19M_3 ),
   .clk_8k_0                   (  ),
   .clk_8k_1                   (  )
    ) ;
*/


/*CHULING_FRAMER_TOP                   INST_FRAMER_TOP_0(
   .reset                            ( GTM_RESET ),
   .clk_sys155m                      ( GTM_CLK155M52 ),
   .clk_sys77m                       ( GS_CLK77M76 ),
   .en_19m_0                         ( timing_framer_en_19m ),
   .en_19m_1                         ( timing_framer_en_19m ),
   .clk_sys19m                       ( timing_framer_clk19m ),
    
   .fp_ppfa_regen                    ( timing_framer_fp8k ),
     
   //*****RX_0*******
   .clk_lin19m_0                     ( RX_CDR_CLK19M_0 ),
   .los_line_in_0                    ( 1'b0 ),
   .loc_line_in_0                    ( 1'b0 ),
   .data_line_in_0                   ( RX_CDR_DATA_0[7:0] ),

   .pohp_loopback_to_bb_0            (  ),
    
   .fp_to_lp_0                       ( rxfp_0 ),
   .j1_to_lp_0                       ( rxj1_0 ),
   .spe_to_lp_0                      ( rxspe_0 ),
   .data_to_lp_0                     ( rxdata_0 ),
    
    //******TX_0*****
   .pohp_loopback_to_lineif_0        (  ),
    
   .tx_fp_to_pohp_0                  ( txfp_0 ),
   .tx_j1_to_pohp_0                  ( txj1_0 ),
   .tx_spe_to_pohp_0                 ( txspe_0 ),
   .tx_data_to_pohp_0                ( txdata_0 ),
    
   .fp_line_out_0                    (  ),
   .data_serial_0                    ( TX_CDR_DATA155M_0 ),
    
    
    //*****RX_1*******
   .clk_lin19m_1                     ( RX_CDR_CLK19M_1 ),
   .los_line_in_1                    ( 1'b0 ),
   .loc_line_in_1                    ( 1'b0 ),
   .data_line_in_1                   ( RX_CDR_DATA_1[7:0] ),

   .pohp_loopback_to_bb_1            (  ),
    
   .fp_to_lp_1                       ( rxfp_1 ),
   .j1_to_lp_1                       ( rxj1_1 ),
   .spe_to_lp_1                      ( rxspe_1 ),
   .data_to_lp_1                     ( rxdata_1 ),
    
    //******TX_1*****
   .pohp_loopback_to_lineif_1        (  ),
    
   .tx_fp_to_pohp_1                  ( txfp_1 ),
   .tx_j1_to_pohp_1                  ( txj1_1 ),
   .tx_spe_to_pohp_1                 ( txspe_1 ),
   .tx_data_to_pohp_1                ( txdata_1 ),
    
   .fp_line_out_1                    (  ),
   .data_serial_1                    ( TX_CDR_DATA155M_1 ),
     
     //***** OH TDM IF ******
   .oh_tdm_clk_pll                   (  ),
     
   .oh_tdm_clk                       (  ),
   .oh_tdm_fp_out                    (  ),
   .oh_tdm_fp_rx                     (  ),
   .oh_rx_data                       (  ),
   .oh_tdm_fp_tx                     (  ),
   .oh_tx_data                       (  ),
    
     //***********
   .ptr_itpre_st_0                   (  ),
   .ptr_itpre_st_1                   (  ),
   .stm1_lof_0                       (  ),
   .stm1_lof_1                       (  ),
   .stm1_los_0                       (  ),
   .stm1_los_1                       (  ),
   .stm1_oof_0                       (  ),
   .stm1_oof_1                       (  ),


   .mpc_rd                           ( MPI_RDEN ),
   .mpc_wr                           ( MPI_WREN ),
   .mpc_addr                         ( MPI_ADDR[7:0] ),
   .mpc_cs_frm_0                     ( MPI_CSB[16] ),
   .mpc_cs_frm_1                     ( MPI_CSB[17] ),
   .mpc_cs_oh_rx_0                   ( MPI_CSB[18] ),
   .mpc_cs_oh_rx_1                   ( MPI_CSB[19] ),
   .mpc_cs_oh_rx_2                   (  ),
   .mpc_cs_oh_rx_3                   (  ),
   .mpc_cs_oh_tx_0                   ( MPI_CSB[20] ),
   .mpc_cs_oh_tx_1                   ( MPI_CSB[21] ),
   .mpc_cs_oh_tx_2                   ( MPI_CSB[22] ),
   .mpc_cs_oh_tx_3                   (  ),
   .mpc_cs_oh_tx_4                   (  ),
    
   .mpc_data_in                      ( MPI_WDATA[15:0] ),
   .mpc_data_out                     ( MPI_RD_FRM_0[15:0] ),
   .frame_int_0                      (  ),
   .frame_int_1                      (  ),

  // interface for CHULING DCC, D1/D2/D3 bytes.
   .CHULING_RDBYTE_EN0               (  ),
   .CHULING_RDBYTE_EN1               (  ),
   .CHULING_RDBYTE_DATA0             (  ),
   .CHULING_RDBYTE_DATA1             (  ),
   .CHULING_TDBYTE_EN0               (  ),
   .CHULING_TDBYTE_EN1               (  ),
   .CHULING_TDBYTE_DATA0             (  ),
   .CHULING_TDBYTE_DATA1             (  )
    );
*/

/*CHULING_FRAMER_TOP                   INST_FRAMER_TOP_1(
   .reset                            ( GTM_RESET ),
   .clk_sys155m                      ( GTM_CLK155M52 ),
   .clk_sys77m                       ( GS_CLK77M76 ),
   .en_19m_0                         ( timing_framer_en_19m ),
   .en_19m_1                         ( timing_framer_en_19m ),
   .clk_sys19m                       ( timing_framer_clk19m ),
    
   .fp_ppfa_regen                    ( timing_framer_fp8k ),
     
   //*****RX_0*******
   .clk_lin19m_0                     ( RX_CDR_CLK19M_2 ),
   .los_line_in_0                    ( 1'b0 ),
   .loc_line_in_0                    ( 1'b0 ),
   .data_line_in_0                   ( RX_CDR_DATA_2[7:0] ),

   .pohp_loopback_to_bb_0            (  ),
    
   .fp_to_lp_0                       ( rxfp_2 ),
   .j1_to_lp_0                       ( rxj1_2 ),
   .spe_to_lp_0                      ( rxspe_2 ),
   .data_to_lp_0                     ( rxdata_2[7:0] ),
    
    //******TX_0*****
   .pohp_loopback_to_lineif_0        (  ),
    
   .tx_fp_to_pohp_0                  ( txfp_2 ),
   .tx_j1_to_pohp_0                  ( txj1_2 ),
   .tx_spe_to_pohp_0                 ( txspe_2 ),
   .tx_data_to_pohp_0                ( txdata_2 ),
    
   .fp_line_out_0                    (  ),
   .data_serial_0                    ( TX_CDR_DATA155M_2 ),
    
    
    //*****RX_1*******
   .clk_lin19m_1                     ( RX_CDR_CLK19M_3 ),
   .los_line_in_1                    ( 1'b0 ),
   .loc_line_in_1                    ( 1'b0 ),
   .data_line_in_1                   ( RX_CDR_DATA_3[7:0] ),

   .pohp_loopback_to_bb_1            (  ),
    
   .fp_to_lp_1                       ( rxfp_3 ),
   .j1_to_lp_1                       ( rxj1_3 ),
   .spe_to_lp_1                      ( rxspe_3 ),
   .data_to_lp_1                     ( rxdata_3[7:0] ),
    
    //******TX_1*****
   .pohp_loopback_to_lineif_1        (  ),
    
   .tx_fp_to_pohp_1                  ( txfp_3 ),
   .tx_j1_to_pohp_1                  ( txj1_3 ),
   .tx_spe_to_pohp_1                 ( txspe_3 ),
   .tx_data_to_pohp_1                ( txdata_3[7:0] ),

   .fp_line_out_1                    (  ),
   .data_serial_1                    ( TX_CDR_DATA155M_3 ),
     
     //***** OH TDM IF ******
   .oh_tdm_clk_pll                   (  ),
     
   .oh_tdm_clk                       (  ),
   .oh_tdm_fp_out                    (  ),
   .oh_tdm_fp_rx                     (  ),
   .oh_rx_data                       (  ),
   .oh_tdm_fp_tx                     (  ),
   .oh_tx_data                       (  ),
    
     //***********
   .ptr_itpre_st_0                   (  ),
   .ptr_itpre_st_1                   (  ),
   .stm1_lof_0                       (  ),
   .stm1_lof_1                       (  ),
   .stm1_los_0                       (  ),
   .stm1_los_1                       (  ),
   .stm1_oof_0                       (  ),
   .stm1_oof_1                       (  ),


   .mpc_rd                           ( MPI_RDEN ),
   .mpc_wr                           ( MPI_WREN ),
   .mpc_addr                         ( MPI_ADDR[7:0] ),
   .mpc_cs_frm_0                     ( MPI_CSB[24] ),
   .mpc_cs_frm_1                     ( MPI_CSB[25] ),
   .mpc_cs_oh_rx_0                   ( MPI_CSB[26] ),
   .mpc_cs_oh_rx_1                   ( MPI_CSB[27] ),
   .mpc_cs_oh_rx_2                   (  ),
   .mpc_cs_oh_rx_3                   (  ),
   .mpc_cs_oh_tx_0                   ( MPI_CSB[28] ),
   .mpc_cs_oh_tx_1                   ( MPI_CSB[29] ),
   .mpc_cs_oh_tx_2                   ( MPI_CSB[30] ),
   .mpc_cs_oh_tx_3                   (  ),
   .mpc_cs_oh_tx_4                   (  ),
    
   .mpc_data_in                      ( MPI_WDATA[15:0] ),
   .mpc_data_out                     ( MPI_RD_FRM_1[15:0] ),
   .frame_int_0                      (  ),
   .frame_int_1                      (  ),

  // interface for CHULING DCC, D1/D2/D3 bytes.
   .CHULING_RDBYTE_EN0               (  ),
   .CHULING_RDBYTE_EN1               (  ),
   .CHULING_RDBYTE_DATA0             (  ),
   .CHULING_RDBYTE_DATA1             (  ),
   .CHULING_TDBYTE_EN0               (  ),
   .CHULING_TDBYTE_EN1               (  ),
   .CHULING_TDBYTE_DATA0             (  ),
   .CHULING_TDBYTE_DATA1             (  )
    );
*/



















//+++++++++++++++++++++++++++++++++++++++++ STM4 TOP Modules +++++++++++++++++++++++++++++++++++++++++++++//
wire                      GTM_LINF_REFCLK311_0;
wire                      GTM_LINF_REFCLK311_45;
wire                      GTM_LINF_REFCLK311_90;
wire                      GTM_LINF_REFCLK311_135;
wire                      GTM_LINF_REFCLK155;
wire                      GTM_SYSCLK19;
wire                      GTM_SYSCLK38;
wire                      GTM_SYSCLK77;
wire                      GTM_SYSCLK155;
wire                      GTM_SYSCLK311;

wire                      GTM_PLL_LINF_REFCLK_LOCKED;
wire                      GTM_PLL_SYSCLK_LOCKED;

reg[3:0]                  GTM_FP_SREG_0, GTM_FP_SREG_1;
reg                       GTM_FP_FLAG_0, GTM_FP_FLAG_1;
reg                       GTM_FILT_FP;
reg[15:0]                 GTM_FILT_CNT19440;
reg                       GTM_SYSFP155;
reg                       GTM_SYSFP77;

wire                      MPI_CLK;
wire[15:0]                MPI_ADDR;
wire[15:0]                MPI_WD;
wire                      MPI_RE;
wire                      MPI_WE;
wire[15:0]                MPI_GLB_REGS_RD, MPI_SOH_0_RD, MPI_SOH_1_RD, MPI_SOH_2_RD, MPI_SOH_3_RD;
wire[15:0]                MPI_FRM_0_RD, MPI_FRM_1_RD, MPI_FRM_2_RD, MPI_FRM_3_RD;
wire                      MPI_GLB_REGS_CS, MPI_SOH_0_CS, MPI_SOH_1_CS, MPI_SOH_2_CS, MPI_SOH_3_CS;
wire                      MPI_FRM_0_CS, MPI_FRM_1_CS, MPI_FRM_2_CS, MPI_FRM_3_CS;
wire[3:0]                 GLBCF_LINF_MODE;



wire[7:0]                 LINF_RXD_0;
wire                      LINF_RXDEN_0;
wire[7:0]                 LINF_RXD_1;
wire                      LINF_RXDEN_1;
wire[7:0]                 LINF_RXD_2;
wire                      LINF_RXDEN_2;
wire[7:0]                 LINF_RXD_3;
wire                      LINF_RXDEN_3;

wire[7:0]                 LINF_TXD_0;
wire[7:0]                 LINF_TXD_1;
wire[7:0]                 LINF_TXD_2;
wire[7:0]                 LINF_TXD_3;


wire[7:0]                 FRM_0_RDATA, FRM_1_RDATA, FRM_2_RDATA, FRM_3_RDATA;
wire                      FRM_0_RDEN, FRM_1_RDEN, FRM_2_RDEN, FRM_3_RDEN;
wire[1:0]                 FRM_0_RFMCNT4, FRM_1_RFMCNT4, FRM_2_RFMCNT4, FRM_3_RFMCNT4;
wire[8:0]                 FRM_0_RFMCNT270, FRM_1_RFMCNT270, FRM_2_RFMCNT270, FRM_3_RFMCNT270;
wire[3:0]                 FRM_0_RFMCNT9, FRM_1_RFMCNT9, FRM_2_RFMCNT9, FRM_3_RFMCNT9;

wire[7:0]                 FRM_0_TDATA, FRM_1_TDATA, FRM_2_TDATA, FRM_3_TDATA;
wire[1:0]                 FRM_0_TFMCNT4, FRM_1_TFMCNT4, FRM_2_TFMCNT4, FRM_3_TFMCNT4;
wire[8:0]                 FRM_0_TFMCNT270, FRM_1_TFMCNT270, FRM_2_TFMCNT270, FRM_3_TFMCNT270;
wire[3:0]                 FRM_0_TFMCNT9, FRM_1_TFMCNT9, FRM_2_TFMCNT9, FRM_3_TFMCNT9;

wire[7:0]                 SOH4_0_RDATA, SOH4_1_RDATA, SOH4_2_RDATA, SOH4_3_RDATA;
wire                      SOH4_0_RDEN, SOH4_1_RDEN, SOH4_2_RDEN, SOH4_3_RDEN;
wire[1:0]                 SOH4_0_RFMCNT4, SOH4_1_RFMCNT4, SOH4_2_RFMCNT4, SOH4_3_RFMCNT4;
wire[8:0]                 SOH4_0_RFMCNT270, SOH4_1_RFMCNT270, SOH4_2_RFMCNT270, SOH4_3_RFMCNT270;
wire[3:0]                 SOH4_0_RFMCNT9, SOH4_1_RFMCNT9, SOH4_2_RFMCNT9, SOH4_3_RFMCNT9;

wire[7:0]                 SOH4_0_TDATA, SOH4_1_TDATA, SOH4_2_TDATA, SOH4_3_TDATA;
wire[1:0]                 SOH4_0_TFMCNT4, SOH4_1_TFMCNT4, SOH4_2_TFMCNT4, SOH4_3_TFMCNT4;
wire[8:0]                 SOH4_0_TFMCNT270, SOH4_1_TFMCNT270, SOH4_2_TFMCNT270, SOH4_3_TFMCNT270;
wire[3:0]                 SOH4_0_TFMCNT9, SOH4_1_TFMCNT9, SOH4_2_TFMCNT9, SOH4_3_TFMCNT9;


wire                      AUPP4_0_FP, AUPP4_1_FP, AUPP4_2_FP, AUPP4_3_FP;
wire                      AUPP4_0_J1, AUPP4_1_J1, AUPP4_2_J1, AUPP4_3_J1;
wire                      AUPP4_0_SPE, AUPP4_1_SPE, AUPP4_2_SPE, AUPP4_3_SPE;
wire[7:0]                 AUPP4_0_DATA, AUPP4_1_DATA, AUPP4_2_DATA, AUPP4_3_DATA;



wire                      BP_TFP;
wire[7:0]                 BP_TDATA_0, BP_TDATA_1, BP_TDATA_2,  BP_TDATA_3;

wire                      BP_RFP;
wire[7:0]                 BP_RDATA_0, BP_RDATA_1, BP_RDATA_2, BP_RDATA_3;

wire                      POH4_TFP;
wire[7:0]                 POH4_TDATA_0, POH4_TDATA_1, POH4_TDATA_2, POH4_TDATA_3;




  assign GTM_RESET   = !debug_reset_cnt[15];


  


GTM_PLL_LINF_REFCLK                   INST_GTM_PLL_LINF_REFCLK(
   .areset                            ( GTM_RESET ),
   .inclk0                            ( CLK_SYS_CLK155M52 ),
   .c0                                ( GTM_LINF_REFCLK155 ),
   .c1                                ( GTM_LINF_REFCLK311_0 ),
   .c2                                ( GTM_LINF_REFCLK311_45 ),
   .c3                                ( GTM_LINF_REFCLK311_90 ),
   .c4                                ( GTM_LINF_REFCLK311_135 ),
   .locked                            ( GTM_PLL_LINF_REFCLK_LOCKED )
   );

/*LINF_PLL                                INST_LINF_PLL(
   .areset                              ( GTM_RESET ),
   .inclk0                              ( CLK_SYS_CLK155M52 ),
   .c0                                  ( GTM_LINF_REFCLK155 ),
   .c1                                  ( GTM_LINF_REFCLK311_0 ),
   .c2                                  ( GTM_LINF_REFCLK311_45 ),
   .c3                                  ( GTM_LINF_REFCLK311_90 ),
   .c4                                  ( GTM_LINF_REFCLK311_135 ),
   .locked                              (  )
   );
*/

GTM_PLL_SYSCLK                        INST_GTM_PLL_SYSCLK(
   .areset                            ( GTM_RESET ),
   .inclk0                            ( CLK_SYS_CLK155M52 ),
   .c0                                ( GTM_SYSCLK19 ),
   .c1                                ( GTM_SYSCLK38 ),
   .c2                                ( GTM_SYSCLK77 ),
   .c3                                ( GTM_SYSCLK155 ),
   .c4                                ( GTM_SYSCLK311 ),
   .locked                            ( GTM_PLL_SYSCLK_LOCKED )
   );

// input FP filter and switch
always @( posedge GTM_RESET or posedge GTM_CLK155M52 ) begin
   if (GTM_RESET==1'b1) begin
      GTM_FP_SREG_0[3:0]                            <= 4'd0;
      GTM_FP_SREG_1[3:0]                            <= 4'd0;
   end
   else begin
      GTM_FP_SREG_0[3:0]                            <= {GTM_FP_SREG_0[2:0], BP_FP_0};
      GTM_FP_SREG_1[3:0]                            <= {GTM_FP_SREG_1[2:0], BP_FP_1};
   end
end

always @( posedge GTM_RESET or posedge GTM_CLK155M52 ) begin
   if (GTM_RESET==1'b1) begin
      GTM_FP_FLAG_0                                 <= 1'b0;
      GTM_FP_FLAG_1                                 <= 1'b0;
   end
   else begin
      GTM_FP_FLAG_0                                 <= GTM_FP_SREG_0[3]==1'b0 && GTM_FP_SREG_0[2]==1'b1;
      GTM_FP_FLAG_1                                 <= GTM_FP_SREG_1[3]==1'b0 && GTM_FP_SREG_1[2]==1'b1;
   end
end

always @( posedge GTM_RESET or posedge GTM_CLK155M52 ) begin
   if (GTM_RESET==1'b1) begin
      GTM_FILT_FP                                   <= 1'b0;
      GTM_FILT_CNT19440[15:0]                       <= 16'd0;
   end
   else begin
      GTM_FILT_FP                                   <= (GTM_FILT_CNT19440[15:0]==16'd19439);
      if ( GTM_FP_FLAG_0==1'b1 ) begin
         if ( GTM_FILT_CNT19440[15:0]!=16'd19437 && GTM_FILT_CNT19440[15:0]!=16'd19438 && GTM_FILT_CNT19440[15:0]!=16'd19439 && GTM_FILT_CNT19440[15:0]!=16'd0 && GTM_FILT_CNT19440[15:0]!=16'd1 && GTM_FILT_CNT19440[15:0]!=16'd2)
            GTM_FILT_CNT19440[15:0]                 <= 16'd0;
         else begin
            if (GTM_FILT_CNT19440[15:0]==16'd19439)
               GTM_FILT_CNT19440[15:0]              <= 16'd0;
            else
               GTM_FILT_CNT19440[15:0]              <= GTM_FILT_CNT19440[15:0] +16'd1;
         end
      end
      else begin
         if (GTM_FILT_CNT19440[15:0]==16'd19439)
            GTM_FILT_CNT19440[15:0]                 <= 16'd0;
         else
            GTM_FILT_CNT19440[15:0]                 <= GTM_FILT_CNT19440[15:0] +16'd1;
      end
   end
end


always @( posedge GTM_RESET or posedge GTM_CLK155M52 ) begin
   if (GTM_RESET==1'b1)
      GTM_SYSFP155                                 <= 1'b0;
   else
      GTM_SYSFP155                                 <= GTM_FILT_CNT19440[15:0]==16'd0 || GTM_FILT_CNT19440[15:0]==16'd1;
end
always @( posedge GTM_RESET or posedge GTM_SYSCLK77 ) begin
   if (GTM_RESET==1'b1)
      GTM_SYSFP77                                  <= 1'b0;
   else
      GTM_SYSFP77                                  <= GTM_SYSFP155;
end

LINF_TOP                              INST_LINF_TOP(
   .LINF_RESET                        ( GTM_RESET ),
   .GTM_SYSCLK77                      ( GTM_SYSCLK77 ),
   .GTM_SYSCLK155                     ( GTM_SYSCLK155 ),
   .GTM_SYSCLK311                     ( GTM_SYSCLK311 ),
   .GTM_LINF_REFCLK311_0              ( GTM_LINF_REFCLK311_0 ),
   .GTM_LINF_REFCLK311_45             ( GTM_LINF_REFCLK311_45 ),
   .GTM_LINF_REFCLK311_90             ( GTM_LINF_REFCLK311_90 ),
   .GTM_LINF_REFCLK311_135            ( GTM_LINF_REFCLK311_135 ),
   .GTM_LINF_REFCLK155                ( GTM_LINF_REFCLK155 ),

   .GLBCF_LINF_MODE                   ( GLBCF_LINF_MODE[3:0] ),

   .AFE_RXD_0                         ( OPT_RXD_3 ),
   .AFE_RXD_1                         ( OPT_RXD_2 ),
   .AFE_RXD_2                         ( OPT_RXD_1 ),
   .AFE_RXD_3                         ( OPT_RXD_0 ),

   .LINF_OUT_RXD_0                    ( LINF_RXD_0[7:0] ),
   .LINF_OUT_RXDEN_0                  ( LINF_RXDEN_0 ),
   .LINF_OUT_RXD_1                    ( LINF_RXD_1[7:0] ),
   .LINF_OUT_RXDEN_1                  ( LINF_RXDEN_1 ),
   .LINF_OUT_RXD_2                    ( LINF_RXD_2[7:0] ),
   .LINF_OUT_RXDEN_2                  ( LINF_RXDEN_2 ),
   .LINF_OUT_RXD_3                    ( LINF_RXD_3[7:0] ),
   .LINF_OUT_RXDEN_3                  ( LINF_RXDEN_3 ),


   .AFE_TXD_0                         ( OPT_TXD_3 ),
   .AFE_TXD_1                         ( OPT_TXD_2 ),
   .AFE_TXD_2                         ( OPT_TXD_1 ),
   .AFE_TXD_3                         ( OPT_TXD_0 ),

   .LINF_IN_TXD_0                     ( LINF_TXD_0[7:0] ),
   .LINF_IN_TXD_1                     ( LINF_TXD_1[7:0] ),
   .LINF_IN_TXD_2                     ( LINF_TXD_2[7:0] ),
   .LINF_IN_TXD_3                     ( LINF_TXD_3[7:0] )
   ) ;



FRM_TOP                               INST_FRM_0(
   .FRM_RESET                         ( GTM_RESET ),
   .FRM_RXCLK                         ( GTM_LINF_REFCLK155 ),
   .FRM_TXCLK                         ( GTM_SYSCLK77 ),

   .MPI_CLK                           ( MPI_CLK ),
   .MPI_ADDR                          ( MPI_ADDR[7:0] ),
   .MPI_CS                            ( MPI_FRM_0_CS ),
   .MPI_WE                            ( MPI_WE ),
   .MPI_WD                            ( MPI_WD[15:0] ),
   .MPI_RD                            ( MPI_FRM_0_RD[15:0] ),
   .MPI_IRQ                           (  ),

   .LINF_IN_RXD                       ( LINF_RXD_0[7:0] ),
   .LINF_IN_RXDEN                     ( LINF_RXDEN_0 ),

   .FRM_OUT_RDATA                     ( FRM_0_RDATA[7:0] ),
   .FRM_OUT_RDEN                      ( FRM_0_RDEN ),
   .FRM_OUT_RFMCNT4                   ( FRM_0_RFMCNT4[1:0] ),
   .FRM_OUT_RFMCNT270                 ( FRM_0_RFMCNT270[8:0] ),
   .FRM_OUT_RFMCNT9                   ( FRM_0_RFMCNT9[3:0] ),

   .LINF_OUT_TXD                      ( LINF_TXD_0[7:0] ),
 
   .FRM_IN_TDATA                      ( FRM_0_TDATA[7:0] ),
   .FRM_IN_TFMCNT4                    ( FRM_0_TFMCNT4[1:0] ),
   .FRM_IN_TFMCNT270                  ( FRM_0_TFMCNT270[8:0] ),
   .FRM_IN_TFMCNT9                    ( FRM_0_TFMCNT9[3:0] ),

   .GLBCF_LINF_MODE                   ( GLBCF_LINF_MODE[0] )
   );
FRM_TOP                               INST_FRM_1(
   .FRM_RESET                         ( GTM_RESET ),
   .FRM_RXCLK                         ( GTM_LINF_REFCLK155 ),
   .FRM_TXCLK                         ( GTM_SYSCLK77 ),

   .LINF_IN_RXD                       ( LINF_RXD_1[7:0] ),
   .LINF_IN_RXDEN                     ( LINF_RXDEN_1 ),

   .FRM_OUT_RDATA                     ( FRM_1_RDATA[7:0] ),
   .FRM_OUT_RDEN                      ( FRM_1_RDEN ),
   .FRM_OUT_RFMCNT4                   ( FRM_1_RFMCNT4[1:0] ),
   .FRM_OUT_RFMCNT270                 ( FRM_1_RFMCNT270[8:0] ),
   .FRM_OUT_RFMCNT9                   ( FRM_1_RFMCNT9[3:0] ),

   .LINF_OUT_TXD                      ( LINF_TXD_1[7:0] ),
 
   .FRM_IN_TDATA                      ( FRM_1_TDATA[7:0] ),
   .FRM_IN_TFMCNT4                    ( FRM_1_TFMCNT4[1:0] ),
   .FRM_IN_TFMCNT270                  ( FRM_1_TFMCNT270[8:0] ),
   .FRM_IN_TFMCNT9                    ( FRM_1_TFMCNT9[3:0] ),

   .GLBCF_LINF_MODE                   ( GLBCF_LINF_MODE[1] )
   );
FRM_TOP                               INST_FRM_2(
   .FRM_RESET                         ( GTM_RESET ),
   .FRM_RXCLK                         ( GTM_LINF_REFCLK155 ),
   .FRM_TXCLK                         ( GTM_SYSCLK77 ),

   .LINF_IN_RXD                       ( LINF_RXD_2[7:0] ),
   .LINF_IN_RXDEN                     ( LINF_RXDEN_2 ),

   .FRM_OUT_RDATA                     ( FRM_2_RDATA[7:0] ),
   .FRM_OUT_RDEN                      ( FRM_2_RDEN ),
   .FRM_OUT_RFMCNT4                   ( FRM_2_RFMCNT4[1:0] ),
   .FRM_OUT_RFMCNT270                 ( FRM_2_RFMCNT270[8:0] ),
   .FRM_OUT_RFMCNT9                   ( FRM_2_RFMCNT9[3:0] ),

   .LINF_OUT_TXD                      ( LINF_TXD_2[7:0] ),
 
   .FRM_IN_TDATA                      ( FRM_2_TDATA[7:0] ),
   .FRM_IN_TFMCNT4                    ( FRM_2_TFMCNT4[1:0] ),
   .FRM_IN_TFMCNT270                  ( FRM_2_TFMCNT270[8:0] ),
   .FRM_IN_TFMCNT9                    ( FRM_2_TFMCNT9[3:0] ),

   .GLBCF_LINF_MODE                   ( GLBCF_LINF_MODE[2] )
   );
FRM_TOP                               INST_FRM_3(
   .FRM_RESET                         ( GTM_RESET ),
   .FRM_RXCLK                         ( GTM_LINF_REFCLK155 ),
   .FRM_TXCLK                         ( GTM_SYSCLK77 ),

   .LINF_IN_RXD                       ( LINF_RXD_3[7:0] ),
   .LINF_IN_RXDEN                     ( LINF_RXDEN_3 ),

   .FRM_OUT_RDATA                     ( FRM_3_RDATA[7:0] ),
   .FRM_OUT_RDEN                      ( FRM_3_RDEN ),
   .FRM_OUT_RFMCNT4                   ( FRM_3_RFMCNT4[1:0] ),
   .FRM_OUT_RFMCNT270                 ( FRM_3_RFMCNT270[8:0] ),
   .FRM_OUT_RFMCNT9                   ( FRM_3_RFMCNT9[3:0] ),

   .LINF_OUT_TXD                      ( LINF_TXD_3[7:0] ),
 
   .FRM_IN_TDATA                      ( FRM_3_TDATA[7:0] ),
   .FRM_IN_TFMCNT4                    ( FRM_3_TFMCNT4[1:0] ),
   .FRM_IN_TFMCNT270                  ( FRM_3_TFMCNT270[8:0] ),
   .FRM_IN_TFMCNT9                    ( FRM_3_TFMCNT9[3:0] ),

   .GLBCF_LINF_MODE                   ( GLBCF_LINF_MODE[3] )
   );


SOH4_TOP                              INST_SOH4_0(
   .SOH4_RESET                        ( GTM_RESET ),
   .SOH4_RCLK                         ( GTM_LINF_REFCLK155 ),
   .SOH4_TCLK                         ( GTM_SYSCLK77 ),

   .MPI_CLK                           ( MPI_CLK ),
   .MPI_ADDR                          ( MPI_ADDR[8:0] ),
   .MPI_CS                            ( MPI_SOH_0_CS ),
   .MPI_WE                            ( MPI_WE ),
   .MPI_WD                            ( MPI_WD[15:0] ),
   .MPI_RD                            ( MPI_SOH_0_RD[15:0] ),

   .FRM4_IN_RDATA                     ( FRM_0_RDATA ),
   .FRM4_IN_RDEN                      ( FRM_0_RDEN ),
   .FRM4_IN_RFMCNT4                   ( FRM_0_RFMCNT4[1:0] ),
   .FRM4_IN_RFMCNT270                 ( FRM_0_RFMCNT270[8:0] ),
   .FRM4_IN_RFMCNT9                   ( FRM_0_RFMCNT9[3:0] ),

   .SOH4_OUT_RDATA                    ( SOH4_0_RDATA[7:0] ),
   .SOH4_OUT_RDEN                     ( SOH4_0_RDEN ),
   .SOH4_OUT_RFMCNT4                  ( SOH4_0_RFMCNT4[1:0] ),
   .SOH4_OUT_RFMCNT270                ( SOH4_0_RFMCNT270[8:0] ),
   .SOH4_OUT_RFMCNT9                  ( SOH4_0_RFMCNT9[3:0] ),

   .SOH4_IN_TDATA                     ( SOH4_0_TDATA[7:0] ),
   .SOH4_IN_TFMCNT4                   ( SOH4_0_TFMCNT4[1:0] ),
   .SOH4_IN_TFMCNT270                 ( SOH4_0_TFMCNT270[8:0] ),
   .SOH4_IN_TFMCNT9                   ( SOH4_0_TFMCNT9[3:0] ),

   .FRM4_OUT_TDATA                    ( FRM_0_TDATA[7:0] ),
   .FRM4_OUT_TFMCNT4                  ( FRM_0_TFMCNT4[1:0] ),
   .FRM4_OUT_TFMCNT270                ( FRM_0_TFMCNT270[8:0] ),
   .FRM4_OUT_TFMCNT9                  ( FRM_0_TFMCNT9[3:0] )
   );
SOH4_TOP                              INST_SOH4_1(
   .SOH4_RESET                        ( GTM_RESET ),
   .SOH4_RCLK                         ( GTM_LINF_REFCLK155 ),
   .SOH4_TCLK                         ( GTM_SYSCLK77 ),

   .FRM4_IN_RDATA                     ( FRM_1_RDATA ),
   .FRM4_IN_RDEN                      ( FRM_1_RDEN ),
   .FRM4_IN_RFMCNT4                   ( FRM_1_RFMCNT4[1:0] ),
   .FRM4_IN_RFMCNT270                 ( FRM_1_RFMCNT270[8:0] ),
   .FRM4_IN_RFMCNT9                   ( FRM_1_RFMCNT9[3:0] ),

   .SOH4_OUT_RDATA                    ( SOH4_1_RDATA[7:0] ),
   .SOH4_OUT_RDEN                     ( SOH4_1_RDEN ),
   .SOH4_OUT_RFMCNT4                  ( SOH4_1_RFMCNT4[1:0] ),
   .SOH4_OUT_RFMCNT270                ( SOH4_1_RFMCNT270[8:0] ),
   .SOH4_OUT_RFMCNT9                  ( SOH4_1_RFMCNT9[3:0] ),

   .SOH4_IN_TDATA                     ( SOH4_1_TDATA[7:0] ),
   .SOH4_IN_TFMCNT4                   ( SOH4_1_TFMCNT4[1:0] ),
   .SOH4_IN_TFMCNT270                 ( SOH4_1_TFMCNT270[8:0] ),
   .SOH4_IN_TFMCNT9                   ( SOH4_1_TFMCNT9[3:0] ),

   .FRM4_OUT_TDATA                    ( FRM_1_TDATA[7:0] ),
   .FRM4_OUT_TFMCNT4                  ( FRM_1_TFMCNT4[1:0] ),
   .FRM4_OUT_TFMCNT270                ( FRM_1_TFMCNT270[8:0] ),
   .FRM4_OUT_TFMCNT9                  ( FRM_1_TFMCNT9[3:0] )
   );
SOH4_TOP                              INST_SOH4_2(
   .SOH4_RESET                        ( GTM_RESET ),
   .SOH4_RCLK                         ( GTM_LINF_REFCLK155 ),
   .SOH4_TCLK                         ( GTM_SYSCLK77 ),

   .FRM4_IN_RDATA                     ( FRM_2_RDATA ),
   .FRM4_IN_RDEN                      ( FRM_2_RDEN ),
   .FRM4_IN_RFMCNT4                   ( FRM_2_RFMCNT4[1:0] ),
   .FRM4_IN_RFMCNT270                 ( FRM_2_RFMCNT270[8:0] ),
   .FRM4_IN_RFMCNT9                   ( FRM_2_RFMCNT9[3:0] ),

   .SOH4_OUT_RDATA                    ( SOH4_2_RDATA[7:0] ),
   .SOH4_OUT_RDEN                     ( SOH4_2_RDEN ),
   .SOH4_OUT_RFMCNT4                  ( SOH4_2_RFMCNT4[1:0] ),
   .SOH4_OUT_RFMCNT270                ( SOH4_2_RFMCNT270[8:0] ),
   .SOH4_OUT_RFMCNT9                  ( SOH4_2_RFMCNT9[3:0] ),

   .SOH4_IN_TDATA                     ( SOH4_2_TDATA[7:0] ),
   .SOH4_IN_TFMCNT4                   ( SOH4_2_TFMCNT4[1:0] ),
   .SOH4_IN_TFMCNT270                 ( SOH4_2_TFMCNT270[8:0] ),
   .SOH4_IN_TFMCNT9                   ( SOH4_2_TFMCNT9[3:0] ),

   .FRM4_OUT_TDATA                    ( FRM_2_TDATA[7:0] ),
   .FRM4_OUT_TFMCNT4                  ( FRM_2_TFMCNT4[1:0] ),
   .FRM4_OUT_TFMCNT270                ( FRM_2_TFMCNT270[8:0] ),
   .FRM4_OUT_TFMCNT9                  ( FRM_2_TFMCNT9[3:0] )
   );
SOH4_TOP                              INST_SOH4_3(
   .SOH4_RESET                        ( GTM_RESET ),
   .SOH4_RCLK                         ( GTM_LINF_REFCLK155 ),
   .SOH4_TCLK                         ( GTM_SYSCLK77 ),

   .FRM4_IN_RDATA                     ( FRM_3_RDATA ),
   .FRM4_IN_RDEN                      ( FRM_3_RDEN ),
   .FRM4_IN_RFMCNT4                   ( FRM_3_RFMCNT4[1:0] ),
   .FRM4_IN_RFMCNT270                 ( FRM_3_RFMCNT270[8:0] ),
   .FRM4_IN_RFMCNT9                   ( FRM_3_RFMCNT9[3:0] ),

   .SOH4_OUT_RDATA                    ( SOH4_3_RDATA[7:0] ),
   .SOH4_OUT_RDEN                     ( SOH4_3_RDEN ),
   .SOH4_OUT_RFMCNT4                  ( SOH4_3_RFMCNT4[1:0] ),
   .SOH4_OUT_RFMCNT270                ( SOH4_3_RFMCNT270[8:0] ),
   .SOH4_OUT_RFMCNT9                  ( SOH4_3_RFMCNT9[3:0] ),

   .SOH4_IN_TDATA                     ( SOH4_3_TDATA[7:0] ),
   .SOH4_IN_TFMCNT4                   ( SOH4_3_TFMCNT4[1:0] ),
   .SOH4_IN_TFMCNT270                 ( SOH4_3_TFMCNT270[8:0] ),
   .SOH4_IN_TFMCNT9                   ( SOH4_3_TFMCNT9[3:0] ),

   .FRM4_OUT_TDATA                    ( FRM_3_TDATA[7:0] ),
   .FRM4_OUT_TFMCNT4                  ( FRM_3_TFMCNT4[1:0] ),
   .FRM4_OUT_TFMCNT270                ( FRM_3_TFMCNT270[8:0] ),
   .FRM4_OUT_TFMCNT9                  ( FRM_3_TFMCNT9[3:0] )
   );





AUPP4_TOP                             INST_AUPP4_0(
   .AUPP_RESET                        ( GTM_RESET ),
   .AUPP_RXCLK                        ( GTM_LINF_REFCLK155 ),
   .AUPP_SYSCLK77                     ( GTM_SYSCLK77 ),
   .AUPP_SYSFP77                      ( GTM_SYSFP77 ),

   .SOH4_IN_RDATA                     ( SOH4_0_RDATA[7:0] ),
   .SOH4_IN_RDEN                      ( SOH4_0_RDEN ),
   .SOH4_IN_RFMCNT4                   ( SOH4_0_RFMCNT4[1:0] ),
   .SOH4_IN_RFMCNT270                 ( SOH4_0_RFMCNT270[8:0] ),
   .SOH4_IN_RFMCNT9                   ( SOH4_0_RFMCNT9[3:0] ),

   .AUPP4_OUT_FP                      ( AUPP4_0_FP ),
   .AUPP4_OUT_J1                      ( AUPP4_0_J1 ),
   .AUPP4_OUT_SPE                     ( AUPP4_0_SPE ),
   .AUPP4_OUT_DATA                    ( AUPP4_0_DATA[7:0] )
   );
AUPP4_TOP                             INST_AUPP4_1(
   .AUPP_RESET                        ( GTM_RESET ),
   .AUPP_RXCLK                        ( GTM_LINF_REFCLK155 ),
   .AUPP_SYSCLK77                     ( GTM_SYSCLK77 ),
   .AUPP_SYSFP77                      ( GTM_SYSFP77 ),

   .SOH4_IN_RDATA                     ( SOH4_1_RDATA[7:0] ),
   .SOH4_IN_RDEN                      ( SOH4_1_RDEN ),
   .SOH4_IN_RFMCNT4                   ( SOH4_1_RFMCNT4[1:0] ),
   .SOH4_IN_RFMCNT270                 ( SOH4_1_RFMCNT270[8:0] ),
   .SOH4_IN_RFMCNT9                   ( SOH4_1_RFMCNT9[3:0] ),

   .AUPP4_OUT_FP                      ( AUPP4_1_FP ),
   .AUPP4_OUT_J1                      ( AUPP4_1_J1 ),
   .AUPP4_OUT_SPE                     ( AUPP4_1_SPE ),
   .AUPP4_OUT_DATA                    ( AUPP4_1_DATA[7:0] )
   );
AUPP4_TOP                             INST_AUPP4_2(
   .AUPP_RESET                        ( GTM_RESET ),
   .AUPP_RXCLK                        ( GTM_LINF_REFCLK155 ),
   .AUPP_SYSCLK77                     ( GTM_SYSCLK77 ),
   .AUPP_SYSFP77                      ( GTM_SYSFP77 ),

   .SOH4_IN_RDATA                     ( SOH4_2_RDATA[7:0] ),
   .SOH4_IN_RDEN                      ( SOH4_2_RDEN ),
   .SOH4_IN_RFMCNT4                   ( SOH4_2_RFMCNT4[1:0] ),
   .SOH4_IN_RFMCNT270                 ( SOH4_2_RFMCNT270[8:0] ),
   .SOH4_IN_RFMCNT9                   ( SOH4_2_RFMCNT9[3:0] ),

   .AUPP4_OUT_FP                      ( AUPP4_2_FP ),
   .AUPP4_OUT_J1                      ( AUPP4_2_J1 ),
   .AUPP4_OUT_SPE                     ( AUPP4_2_SPE ),
   .AUPP4_OUT_DATA                    ( AUPP4_2_DATA[7:0] )
   );
AUPP4_TOP                             INST_AUPP4_3(
   .AUPP_RESET                        ( GTM_RESET ),
   .AUPP_RXCLK                        ( GTM_LINF_REFCLK155 ),
   .AUPP_SYSCLK77                     ( GTM_SYSCLK77 ),
   .AUPP_SYSFP77                      ( GTM_SYSFP77 ),

   .SOH4_IN_RDATA                     ( SOH4_3_RDATA[7:0] ),
   .SOH4_IN_RDEN                      ( SOH4_3_RDEN ),
   .SOH4_IN_RFMCNT4                   ( SOH4_3_RFMCNT4[1:0] ),
   .SOH4_IN_RFMCNT270                 ( SOH4_3_RFMCNT270[8:0] ),
   .SOH4_IN_RFMCNT9                   ( SOH4_3_RFMCNT9[3:0] ),

   .AUPP4_OUT_FP                      ( AUPP4_3_FP ),
   .AUPP4_OUT_J1                      ( AUPP4_3_J1 ),
   .AUPP4_OUT_SPE                     ( AUPP4_3_SPE ),
   .AUPP4_OUT_DATA                    ( AUPP4_3_DATA[7:0] )
   );




POH4_TOP                              INST_POH4_TOP_0(
   .POH4_RESET                        ( GTM_RESET ),
   .POH4_SYSCLK77                     ( GTM_SYSCLK77 ),

   .AUPP4_IN_RDATA                    (  ),
   .AUPP4_IN_FP                       (  ),

   .POH4_IN_TDATA                     ( POH4_TDATA_0[7:0] ),
   .POH4_IN_TFP                       ( POH4_TFP ),


   .SOH4_OUT_TDATA                    ( SOH4_0_TDATA[7:0] ),
   .SOH4_OUT_TFMCNT4                  ( SOH4_0_TFMCNT4[1:0] ),
   .SOH4_OUT_TFMCNT270                ( SOH4_0_TFMCNT270[8:0] ),
   .SOH4_OUT_TFMCNT9                  ( SOH4_0_TFMCNT9[3:0] )

   );
POH4_TOP                              INST_POH4_TOP_1(
   .POH4_RESET                        ( GTM_RESET ),
   .POH4_SYSCLK77                     ( GTM_SYSCLK77 ),

   .AUPP4_IN_RDATA                    (  ),
   .AUPP4_IN_FP                       (  ),

   .POH4_IN_TDATA                     ( POH4_TDATA_1[7:0] ),
   .POH4_IN_TFP                       ( POH4_TFP ),
// .POH4_IN_TDATA                     ( AUPP4_1_DATA[7:0] ),
// .POH4_IN_TFP                       ( AUPP4_1_FP ),


   .SOH4_OUT_TDATA                    ( SOH4_1_TDATA[7:0] ),
   .SOH4_OUT_TFMCNT4                  ( SOH4_1_TFMCNT4[1:0] ),
   .SOH4_OUT_TFMCNT270                ( SOH4_1_TFMCNT270[8:0] ),
   .SOH4_OUT_TFMCNT9                  ( SOH4_1_TFMCNT9[3:0] )

   );
POH4_TOP                              INST_POH4_TOP_2(
   .POH4_RESET                        ( GTM_RESET ),
   .POH4_SYSCLK77                     ( GTM_SYSCLK77 ),

   .AUPP4_IN_RDATA                    (  ),
   .AUPP4_IN_FP                       (  ),

   .POH4_IN_TDATA                     ( POH4_TDATA_2[7:0] ),
   .POH4_IN_TFP                       ( POH4_TFP ),


   .SOH4_OUT_TDATA                    ( SOH4_2_TDATA[7:0] ),
   .SOH4_OUT_TFMCNT4                  ( SOH4_2_TFMCNT4[1:0] ),
   .SOH4_OUT_TFMCNT270                ( SOH4_2_TFMCNT270[8:0] ),
   .SOH4_OUT_TFMCNT9                  ( SOH4_2_TFMCNT9[3:0] )

   );
POH4_TOP                              INST_POH4_TOP_3(
   .POH4_RESET                        ( GTM_RESET ),
   .POH4_SYSCLK77                     ( GTM_SYSCLK77 ),

   .AUPP4_IN_RDATA                    (  ),
   .AUPP4_IN_FP                       (  ),

   .POH4_IN_TDATA                     ( POH4_TDATA_3[7:0] ),
   .POH4_IN_TFP                       ( POH4_TFP ),


   .SOH4_OUT_TDATA                    ( SOH4_3_TDATA[7:0] ),
   .SOH4_OUT_TFMCNT4                  ( SOH4_3_TFMCNT4[1:0] ),
   .SOH4_OUT_TFMCNT270                ( SOH4_3_TFMCNT270[8:0] ),
   .SOH4_OUT_TFMCNT9                  ( SOH4_3_TFMCNT9[3:0] )

   );




   assign  POH4_TFP              = BP_RFP;
   assign  POH4_TDATA_0[7:0]     = BP_RDATA_0[7:0];
   assign  POH4_TDATA_1[7:0]     = BP_RDATA_1[7:0];
   assign  POH4_TDATA_2[7:0]     = BP_RDATA_2[7:0];
   assign  POH4_TDATA_3[7:0]     = BP_RDATA_3[7:0];

   assign  BP_TFP                = AUPP4_0_FP;
   assign  BP_TDATA_0[7:0]       = AUPP4_0_DATA[7:0];
   assign  BP_TDATA_1[7:0]       = AUPP4_1_DATA[7:0];
   assign  BP_TDATA_2[7:0]       = AUPP4_2_DATA[7:0];
   assign  BP_TDATA_3[7:0]       = AUPP4_3_DATA[7:0];


BP_TOP                               INST_BP_TOP(
   .BP_RESET                         ( GTM_RESET ),
   .BP_SYSCLK155                     ( GTM_CLK155M52 ),
   .GS_CLK38M88                      ( GS_CLK38M88 ),
   .BP_SYSCLK77                      ( GS_CLK77M76 ),
   .BP_GX_RFCLK155                   ( BP_RF_CLK155M52 ),

   .BP_TXD_0                         ( BP_TXD_0 ),
   .BP_TXD_1                         ( BP_TXD_1 ),

   .BP_IN_TFP                        ( BP_TFP ),
   .BP_IN_TDATA_0                    ( BP_TDATA_0[7:0] ),
   .BP_IN_TDATA_1                    ( BP_TDATA_1[7:0] ),
   .BP_IN_TDATA_2                    ( BP_TDATA_2[7:0] ),
   .BP_IN_TDATA_3                    ( BP_TDATA_3[7:0] ),


   .BP_RXD_0                         ( BP_RXD_0 ),
   .BP_RXD_1                         ( BP_RXD_1 ),
   .BP_OUT_RFP                       ( BP_RFP ),
   .BP_OUT_RDATA_0                   ( BP_RDATA_0[7:0] ),
   .BP_OUT_RDATA_1                   ( BP_RDATA_1[7:0] ),
   .BP_OUT_RDATA_2                   ( BP_RDATA_2[7:0] ),
   .BP_OUT_RDATA_3                   ( BP_RDATA_3[7:0] )
   );



//  ++++++++++++++++++      MPI Interface Modules      ++++++++++++++++++  //
  assign MPI_CLK       = GS_CLK77M76;
STM4_MPI                             INST_STM4_MPI(
   .MPI_RESET                        ( GTM_RESET ),
   .MPI_CLK                          ( MPI_CLK ),
   .CPU_ADDR                         ( CPU_A[15:0] ),
   .CPU_RW                           ( CPU_RW ),
   .CPU_CSN                          ( CPU_CSN ),
   .CPU_DATA                         ( CPU_D[15:0] ),

   .MPI_ADDR                         ( MPI_ADDR[15:0] ),
   .MPI_WD                           ( MPI_WD[15:0]),
   .MPI_RE                           ( MPI_RE ),
   .MPI_WE                           ( MPI_WE ),
   .MPI_GLB_REGS_RD                  ( MPI_GLB_REGS_RD[15:0] ),
   .MPI_SOH_0_RD                     ( MPI_SOH_0_RD[15:0] ),
   .MPI_SOH_1_RD                     ( MPI_SOH_1_RD[15:0] ),
   .MPI_SOH_2_RD                     ( MPI_SOH_2_RD[15:0] ),
   .MPI_SOH_3_RD                     ( MPI_SOH_3_RD[15:0] ),
   .MPI_FRM_0_RD                     ( MPI_FRM_0_RD[15:0] ),
   .MPI_FRM_1_RD                     ( MPI_FRM_1_RD[15:0] ),
   .MPI_FRM_2_RD                     ( MPI_FRM_2_RD[15:0] ),
   .MPI_FRM_3_RD                     ( MPI_FRM_3_RD[15:0] ),
   .MPI_GLB_REGS_CS                  ( MPI_GLB_REGS_CS ),
   .MPI_SOH_0_CS                     ( MPI_SOH_0_CS ),
   .MPI_SOH_1_CS                     ( MPI_SOH_1_CS ),
   .MPI_SOH_2_CS                     ( MPI_SOH_2_CS ),
   .MPI_SOH_3_CS                     ( MPI_SOH_3_CS ),
   .MPI_FRM_0_CS                     ( MPI_FRM_0_CS ),
   .MPI_FRM_1_CS                     ( MPI_FRM_1_CS ),
   .MPI_FRM_2_CS                     ( MPI_FRM_2_CS ),
   .MPI_FRM_3_CS                     ( MPI_FRM_3_CS )
   ) ;


STM4_GLB_REGS                        INST_STM4_GLB_REGS(
   .MPI_RESET                        ( GTM_RESET ),

   .MPI_CLK                          ( MPI_CLK ),
   .MPI_ADDR                         ( MPI_ADDR[7:0] ),
   .MPI_CS                           ( MPI_GLB_REGS_CS ),
   .MPI_WE                           ( MPI_WE ),
   .MPI_WD                           ( MPI_WD[15:0] ),
   .MPI_RD                           ( MPI_GLB_REGS_RD[15:0] ),

   .GLBCF_LINF_MODE                  ( GLBCF_LINF_MODE[3:0] )
    ) ;

endmodule
